Testing device for differential amplifiers

ABSTRACT

A device for verifying the response time of a differential amplifier, wherein recurrent pulses are applied to input terminals of a differential amplifier under test and a visual testing instrument is coupled to respond to such input pulses and the consequent output pulses of the amplifier to provide a display of the response time of the amplifier, and wherein a signal is applied between the two input terminals of the amplifier to effectively cancel the unbalanced voltage between such two terminals in the absence of test pulses.

United States Patent [191' Bernard 1 Feb. 27, 1973 [54] TESTING DEVICEFOR DIFFERENTIAL AMPLIFIERS [75] Inventor: Marcel Bernard, Angers,France [73] Assignee: Societe Industrielle Honeywell Bull (SocieteAnonyme), Paris, France 22 Filed: May 24,1971

21 Appl.No.: 146,404

[30] Foreign Application Priority Data OTHER PUBLICATIONS Woelkers,Circuit for Measuring the Turnon and Turnoff Delays of a Test Unit, IBMTechnical Disclosure Bulletin, July 1964, pp. 130, 131.

Woodard, Time Delay Measuring System, IBM Technical Disclosure Bulletin,pp 1541, 1542, April 1967.

Plumb, Teamwork Streamlines Differential Amplifier Tests, Electronics,Sept. 15, 1969, pp 132-135.

Primary ExaminerStanley T. Krawczewicz Attorney-Ronald T. Reiling, FredJacob and Lewis P. Elbinger [57] ABSTRACT A device for verifying theresponse time of a differential amplifier, wherein recurrent pulses areapplied to input terminals of a differential amplifier under test and avisual testing instrument is coupled to respond to such input pulses andthe consequent output pulses of the amplifier to provide a display ofthe response time of the amplifier, and wherein a signal is appliedbetween the two input terminals of the amplitier to effectively cancelthe unbalanced voltage between such two terminals in the absence of testpulses.

8 Claims, 8 Drawing Figures ATT EST

SCH

PATENTEDFEBZYISH SHEET 2 [1F 4 LALA INVE NTOR WM) @U BY/Z w ATTJRN EYTESTING DEVICE FOR DIFFERENTIAL AMPLIFIERS BACKGROUND OF THE INVENTIONThis invention relates to a testing device for verifying Differentialamplifiers mustusually meet a set of severe specifications to be usedwith assurance in modern, high performance electronic circuits. Thetesting devices of the prior art usually employed for verifying thatthese specifications are met are quite complex, and, therefore, arebulky and of costly construction. Moreover, they most often lackflexibility and thus can be operated only with a single type of visualtesting instrument.

Accordingly it is the object of the present invention to provide atestingv device for verifying the response time of differentialamplifiers that is relatively simple in construction, reasonablycompact, and demonstrates a certain degree of flexibility in use.

The testing device of the invention is intended to be operated withvarious visual indicating means. In a first instance, the device can beconnected to an oscillosco'pe to perform two successive measurements ofresponse time upon the applicationof suitable signals to the inputterminals of the amplifier under test. In a second instance, the devicecan be connected to automatic apparatus which enables simultaneouslyperforming the above-mentioned two measurements, resulting in anadditional saving of time.

SUMMARY OF THE INVENTION In accordance with the invention, a testingdevice is provided for measuring the response time of a transistorizeddifferential amplifier upon the applica tion of a recurrent transientsignal to one of its two signal input terminals. The testing devicecomprises connection means providing access to first and second signalinput terminals, a signal output terminal, and a control input terminalof an amplifier to be tested, and further providing suitable voltages ofproper polarity to such amplifier. The testing device further comprisescircuit means for coupling the second signal input terminal and thesignal output terminal in 'an inverse feedback loop to efi'ectivelycancel the unbalanced voltage between the two input terminals intheabsence of an input signal. A generator of recurrent signal pulses isconnectedto apply such signal pulses to the first signal input terminalof the amplifier under test, each such signal pulse having a durationmuch shorter than its recurrence period. In addition, the testing devicecomprises means for connecting the first signal input terminal and thesignal output terminal of the amplifier under test to visual testinginstruments.

Each amplifier of the type under consideration is provided in the formof a module pluggable into the sockets of a suitable support of thetesting device. This amplifier is provided with a control input terminalfor receiving a suitable voltage pulse which during its presence,inhibits the operation of the amplifier. The signal pulse generator isadapted to apply inhibiting pulses to the control input terminalconcurrently with the signalpulses applied to the first signal inputterminal. The above-described arrangement can be operated, as such, withan automatically controlled apparatus provided for this purpose.

In the instance wherein the testing device is utilized in associationwith a dual-beam oscilloscope, switching means are provided for couplinga first vertical input terminal of the oscilloscope either to the firstsignal input terminal of the amplifier or to the control input terminalthereof. The second vertical input terminal of the oscilloscopecontinues to be connected to the output terminal of the amplifier.During a first measurement, the visual displaying of the output signalenables rapidly evaluating the response time in relation to the trailingedge of an input pulse, and duringagsecond measurement, the visualdisplaying of the output signal enables evaluating the response time inrelation to the trailing edge of an inhibiting pulse.

BRIEF DESCRIPTION OF THE DRAWING The invention will be described withreference to the accompanying drawing, wherein:

FIG. 1 is a simplified schematic diagram of an arrangement for measuringresponse time, according to the invention;

FIG. 2 is a schematic diagram of an adaptation board which is part ofthe testing device;

FIG. 3 is a logical schematic diagram of a signal generator adapted tobe utilized in the testing device;

FIG. 4 is a schematic diagram of a multivibrator which is part of thesignal generator;

FIG. 5 is a timing diagram of signals furnished by the signal generatorand signals present at certain points therein;

FIG. 6 is a timing diagram of signals present in a DESCRIPTION OF THEPREFERRED EMBODIMENT FIG. 1 illustrates in part a measuring arrangementin which are represented symbolically only a differential amplifier ATto be tested, switches CR1 and CR2, and a dual-beam oscilloscope 10. Thetesting device proper is not shown in this figure.

During a first measurement switches CR1 and CR2, manually actuated andmechanically coupled, are in the position shown in the figure. At thistime a first signal input terminal E1 of the amplifier AT under test isconnected to a first vertical input terminal EVl of oscilloscope 10.During this time input terminal E1 receives test pulses through a meansATT, shown symbolically as a resistor, but which, in actuality, consiststerminal E2 of amplifier AT also receives a series of test pulsesthrough another means ATT, which is similar to the above-mentioned meansATT.

Signal output terminal S1 of amplifier AT is connected directly to thesecond vertical input terminal EV2 of the oscilloscope. The multiplegenerator which furnishes the above-mentioned test pulses also generatessynchronization (sync) pulses, which are transmitted by switch CR2 to asynchronization (sync) input terminal 11 of the oscilloscope and whichtrigger the horizontal sweep at desired times.

This multiple generator also generates inhibiting pulses, termed strobepulses which are applied to a control input terminal EST of amplifierAT. These inhibiting pulses are only displayed during the secondmeasurement; i.e., when the movable contacts of switches CR1 and CR2occupy their opposite positions, wherein the first vertical inputterminal EVl is connected to control input terminal EST. When switch CR2is reversed, the inhibiting pulses are applied to sync input terminal 11of oscilloscope 10.

The actual structure of the testing device will be explained byreference to Figs. 2 and 3. Figure 2 is a schematic diagram of a testingboard whose physical realization may vary according to need.Nevertheless, such board will bear a module support provided withsockets disposed to receive the 'pins of a miniaturized integratedcircuit module. Although certain modules of this type may incorporatetwo amplifiers, only the testing of a single differential amplifier willbe considered herein. Therefore, the module to be tested has pins whichcorrespond to first and second signal input terminals El and E2, acontrol input terminal EST, a signal output terminal S1, and supplyterminals 12, 13 and 14. It is presumed that these supply terminals willbe connected to suitable electric potential sources, such that terminal12 receives a voltage +V1, for example of +l2v terminal 13 receives azero, or ground, voltage, and terminal 14 receives a voltage V3, forexample of 6v.

The testing board comprises an amplifier AF, also of the differentialtype, which is incorporated in an inverse feedback loop intended tocompensate for the unbalanced or offset voltage across signal inputterminals of the amplifier under test outside the repeated measurementperiods. Thus, when no signal is applied to input terminals El and E2 ofeach amplifier under test, an unbalanced difference of voltage andcurrent can exist between these two input terminals. While theunbalanced, current may be negligible under certain conditions, it isimportant that the unbalanced voltage, which is variable although veryweak, be cancelled during the relatively long interval separating twosuccessive measurement periods.

For this purpose, output terminal S1 of the amplifier AT under test isconnected to a first input terminal 15 of amplifier AF and outputterminal S2 of amplifier AF 3 is connected through a resistor R3 tosecond signal input terminal E2 of amplifier AT. A second input terminal16 of amplifier AF is connected to a voltage source 17. Source 17, shownas a battery, must supply a stable regulated voltage +VC, with a valueof +1.4v which is the value of voltage which normally should be presentat output terminal S1 of amplifier AT in the absence of signals on theinput terminals thereof. Assuming that amplifier AF is also suppliedwith suitable voltages of proper polarity, it actually compares thevoltages received on its two input terminals. A capacitor 18 connectedbetween output terminal S2 and ground performs an integration function.

Output terminal S1 is connected to terminal 14 through a load resistorR5. In order to prevent input terminals 15 and 16 from being subjectedto an .extremely large potential difference when an amplifier module ATis removed from the support, these input terminals are connectedtogether by four silicon diodes, such as diodes 19, connected in series.

Input terminals E1 and E2 of amplifier AT are connected to groundthrough respective resistors R2 and R4. Resistors R2 and R4 haverelatively small values of resistance, for example 10 ohms, in orderthat the ef fects of an unbalanced current, described above, benegligible.

In the voltage divider formed by resistors R3 and R4,

the ratio of their resistances (R3/R4) is approximately- 1000,considering the voltage gains in the loop of amplifiers AT and AF.

The means ATT of Fig. l, as shown in Fig. 2, comprises two voltagecalibrators, designated by the reference numerals 20 and 21, and the twovoltage dividers formed respectively by resistors R1 and R2 and byresistors R6 and R4. Calibrator 20 comprises a transistor 22, whosecollector is connected to a terminal 23, which is assumed to beconnected to a source of steady voltage +V2, for example of +5v. Theemitter of transistor 22 is connected to ground through a load resistorR7 and the series-connected resistors R1 and R2. The base of transistor22 is connected to an input terminal 24 through a resistor R8 and toground through a resistor R9, a diode 25, and a resistor RV connected inseries. Diode 25 serves to compensate for temperature variations whichmay affect the baseemitter voltage of transistor 22.

The ratio of the resistances (RI/R2) of resistors R1 and R2 isapproximately 100. When resistor RV has been suitably adjusted and inputterminal 24 receives a positive pulse of 3.5v amplitude from an outputterminal SA of the signal generator, the voltage developed acrossresistor R7 is 1.5V and that applied to input terminal E1 is 15millivolts.

The ratio of the resistances (R6/R4) of resistors R6 and R4 isapproximately 300. When calibrator 21 has been suitably adjusted and itsinput terminal- 26 receives a positive pulse of 3.5V amplitude, thevoltage developed at the output terminal of calibrator 21 is also 1.5v,but the voltage applied to input terminal E2 is only 5 millivolts.

The signal generator included in the testing device will be described byreference to FIG. 3. In this signal generator, a first group of circuitsforms a multistable device 27 and another group of circuits forms adelay unit 28.

Multistable device 27 basically comprises two registers 29 and 30interconnected by several logic circuits. Registers 29 and 30 areidentical and each comprises four stages, or bit positions. Each suchregister may be of a type actually available in the form of integratedcircuits of transistors. Each register stage is provided with one inputterminal, such as input terminals 31 and 32,'and one output terminal,such as terminals 33 and 34. The output terminals of register 30 aredirectly connected to the corresponding input terminals of register 29.For example, output terminal 34 of stage A2 is directly connected toinput tenninal 31 of stage Al. Registers 29 and 30 are so constructedsuch that the logical states at the input terminals are transferred tothe corresponding output terminals when a positive clock pulse isapplied to a common input terminal, such as terminals C29 and C30.

The output signals SA, SB, SC and SD of register 29 are utilized tofurnish appropriate signals for the testing board previously describedand for the visual testing instruments.

The different stable states of multistable device 27 are determinedbylogic circuits which appropriately connect the output terminals ofregister 29 to the input terminals ofregister 30. Thus, a NAND circuitETl has two input leads which are connected respectively to outputterminals SA and SB. The output lead of NAND circuit ETl is connectedthrough an inverter 12 to the input terminal of stage C2. Thedesignations of the logical circuits utilized herein are valid forpositive binary logic, i.e. that binary logic wherein the value of thebinary 1 is represented by a positive, or high level, voltage andwherein the binary zero is represented by a low level voltage, which maybe zero or negligible in the logical circuit.

A single inverter 13 connects output terminal SB of stage B1 to theinput terminal of stage A2. The output terminal SC of stage Cl isconnected through an inverter 14 to the input terminal of stage D2.Finally the input terminal of stage B2 is connected to the output leadof a NAND circuit ET2. NAND circuit ET2 has three input leads, of whichthe first is connected through an inverter 11 to output terminal SA, thesecond is connected to the output lead of inverter 14, and the third isconnected to the output terminal SD of stage D1.

Delay unit 28 comprises basically an astable multivibrator 35, twomonostable circuits 36 and 37 connected in succession and logic circuitsconnected as shown in Fig. 3. Output terminal SB of register 29 isconnected through an inverter 15 to the input terminal of the firstmonostable 36. A NAND circuit ET3 has two input leads which areconnected respectively to the output terminals of monostables 36 and 37.The output lead 38 of NAND circuit ET3 is directly connected to theinput terminal of multivibrator 35 and is connected through an inverter16 to one input lead of a NAND circuit ET4. The other input lead of NANDcircuit ET4 is connected by an inverter 17 to the output terminal MV ofmultivibrator 35. Theoutput lead 39 of NAND circuit ET4 delivers clockpulses to input terminal C30 of register 30. The output lead 40 of aninverter 18 delivers clock pulses, which are complementary to thosedelivered by NAND circuit ET4, to input terminal C29 of register 29.

Monostables 36 and 37 may be identical and of a well-known type whereinthe output terminal delivers a positive output voltage when themonostable is in its rest state. The output voltage drops to a low levelwhen the monostable input terminal is subjected to a step voltage ofpositive sense remaining at such low level during a quasi-stable statedetermined by a time-constant network.

The schematic diagram of multivibrator 35 is given by Fig. 4. Thiswell-known circuit is supplied with a positive voltage +V2 and comprisesbasically two transistors Q1 and O2, to which are connected resistorsRIO-R13 and capacitors C1 and C2. A transistor Q0 served to block orunblock the multivibrator according to whether the voltage applied toterminal 38 is high or low. During the greater part of the time thisvoltage is +3.5v, which causes diode D1 to be cutoff and transistor O0to receive through resistor R14 and silicon diodes D2 and D3 a basecurrent sufficient for saturation. The collector voltage of transistorQois thereby sufficiently low to block, or cutoff, transistor Q1, sothat transistor O2 is saturated. However, at the start of a measurementperiod, which will be defined hereinafter, the voltage applied toterminal 38 becomes substantially zero, whereupon diode D1 draws all ofthe current furnished by resistor R14 and diodes D2 and D3 andtransistor ()0 are cutoff. Multivibrator 35 is thereby unblocked andpulses appear at output terminal MV.

The general operation may be described in detail by reference to FIGS.3, 5 and 6. The arrangement of the signal generator described above issuch that when voltage is supplied thereto, multistable device 27 passesthrough a sequence of state changes which are immediately followed by asequence of states, which are necessary for the continuous operation ofthe testing device.

Delay unit 28 provides the signal generator with a recurrence period ofduration P2 (waveform l6) in which is included a measurement period ofduration Pl.

Assume, now, that at a time t0 monostable 37 returns to its rest state(waveform MS2, FIG. 6). The two input signals of NAND circuit ET3 arenow at the positive, or high, level, whereupon the voltage on terminal38 becomes zero, or approximately zero, and multivibrator 38 becomesunblocked. One input lead of NAND circuit ET4 is now at the positivelevel forthe duration P1 (waveform 16). The other input lead of circuitET4 receives the pulses generated by multivibrator 35, after inversionby inverter 17. Accordingly, NAND circuit ET4 delivers a first series ofclock pulses (waveform 39), which are applied to register 30 ofmultistable device 27, and a second series of inverted clock pulses(waveform 40) which are applied to register 29.

The arrangement of multistable device 27 is such that a positive pulseof 3.5v appears at output terminal SA (waveform SA-El, FIG. 5) andcontinues through periods p2 and p3, terminating at time t3. A secondpositive pulse of 3.5V then appears at output terminal SB at time t2,and continues until time t6. A third positive pulse of 3.5v next appearson output terminal SC from time :3 to time 14. Stage D1 of register 29is specially designed so that the voltage on output terminal SD isnormally at the level of +V2, or 5v, whereby a negative pulse ofapproximately 5v amplitude appears at output terminal 50 from time t4through time t5.

At time t6, when output terminal SB returns to zero voltage, this stepvoltage of negative sense is transformed by inverter 15 to a positivestep voltage, which triggers monostable 36. When the output signal MSlof monostable 36 returns again to its high voltage level, the resultingpositive step triggers the operation of monostable 37 (waveform MS2).The time-constant networks of monostables 36 and 37 are designed so thatthe total duration of the negative pulses they provide determines aperiod, termed compensation period," of which the total duration isP2-P1. During this compensation period, the voltages at output terminalsSASD do not vary. When, again the second monostable 37 returns to itsrest state, a new measurement period starts.

Since output terminal SA, FIG, 3, is connected to input terminal 24 ofcalibrator 20, FIG. 2, the first signal input terminal E1 of theamplifier AT under test receives a positive pulse 41, reduced to 15millivolts, during interval tl-t3 of each measurement period Pl. If

switches CR1 and CR2 are in the positions shown in FIG. 1, this receivedpulse is also applied to input terminal EVl of oscilloscope 10.

Since output terminal SB is connected to input terminal 26 of calibrator21, the second signal input terminal E2 of amplifier AT receives apositive pulse 42 of 5 millivolts during the interval :2 t6 of eachmeasurement period.

Since output terminal SC is connected to the upper contact of switchCR2, FIG. 1, the sync input terminal 11 of the oscilloscope receives apositive synchronization pulse 43 between times t3 and 14 of eachmeasure ment period.

Since output terminal SD is directly connected to the control inputterminal EST of amplifier AT, the latter receives a negative inhibitingpulse 44 between times t4 and t5 of each measurement period.

Certain characteristics of the type of differential amplifier subjectedto the testing described herein are as follows. As mentioned previously,output terminal 81 is normally at a voltage of +1.4v, termed the logicthreshold level, when the input voltages are zero. A positive voltage ofa few millivolts on input terminal E1, the inverting input terminal,reduces the output voltage to approximately 0.5v, whereas a similarlysmall negative voltage on the same input terminal causes the outputvoltage level to rise to approximately +4v. When these same inputvoltages are applied to input terminal E2, termed the non-invertinginput terminal, voltage levels result on output terminal S1 which arethe inverse of those previously described. However, amplifier AT isoperative only when a voltage of +5v is applied to control inputterminal EST. When the voltage on input terminal EST is reduced to zero,during an inhibiting pulse, amplifier AT becomes completely inoperativeand the level of its output voltage remains at approximately 0.5v.

During the first measurement operation switches CR1 and CR2 are in theposition shown in Fig. l, and there can be observed on the oscilloscopescreen both the falling trailing edge 41A of input pulse 41, FIG. 7, andthe trace 45 of the output voltage. Since horizontal time referencemarks and vertical voltage level reference marks have been preinscribedon the screen, it is easy to evaluate the response time TRl betweenpulse edge 41A and the instant when trace 45 crosses a level 46, whichcan be related to the logic threshold level previously described. Pulseedge 41A corresponds substantially to time 13 of FIG. 5 and the leadingedge of pulse 43 of positive sense which triggers the horizon tal sweepat the same instant.

The amplitude of pulse 41 is relatively great in order to produce a highdegree of saturation in the semiconductors of the amplifier which areinvolved. The amplitude of pulse 42 is smaller, but is sufficient forthe output voltage to reach its maximum level after the termination ofpulse 41.

i For performing the second measuring operation, the position ofswitches CR1 and CR2 are reversed. The only changes in the circuit arethat input terminals EVl and 11 of oscilloscope now receive inhibitingpulse 44, FIG. 5. During the occurrence of the inhibiting pulse theoutput voltage of amplifier AT is reduced to approximately 0.5v At thetermination of the inhibiting pulse, time :5, the amplifier returns toits operative state. The rear edge, of positive sense, of the inhibitingpulse triggers the horizontal sweep of oscilloscope l0 and there canthen be observed, Fig. 8, both this rear edge 44A and the trace 47 ofthe output voltage. In a manner similar to that described previously, itis easy to evaluate the response time TRS between the beginning of therise of pulse edge 44A and the instant when trace 47 crosses the logicthreshold level 46.

For the type of differential amplifier considered herein, the maximumvalue of response time TRl is fixed, for example at 50 nanoseconds, andthat of response time TRS is fixed, for example at 20 nanoseconds. Thetwo measurement operations each take only a few seconds.

In the symmetrical multivibrator 35 of FIG. 4, the duration of the clockpulses depends primarily on the equal resistors R10 and R12 and equalcapacitors C1 and C2. For example, if the duration of a clock pulse is1.8 microseconds, the total interval P1 of a measurement period is 19.8microseconds. Moreover, the two 'monostables 36 and 37 of delay unit 28,FIG. 3, are

designed so that the duration of the compensation period P2 P1 is 560microseconds. The recurrence period, therefore, is approximately 580microseconds in the example presented. These values correspond to thecondition that the recurrence period P2 of the signals applied to theinput terminals of the amplifier under test be at least 20 to 25 timeslarger than the duration of the measurement period P1. The value ofcapacitor 18, Fig. 2, must be sufficiently great so that at outputterminal S2, the compensating voltage of the unbalanced voltage of inputterminals E1 and E2 varies very little during the course of ameasurement period There is sufficient time for the equilibrium of theinput voltages to be re-established during the relatively longcompensation period.

When the testing device is operated with automatic apparatus, the lattercomprises special input terminals which are connected to input terminalsE1 and EST and output terminal S1 of the amplifier under test, whereasthe synchronization pulse provided at output terminal SC of thegenerator may or may not be employed according to the type of the.automatic apparatus.

It is understood that a signal generator different from that describedpreviously herein can be employed, provided that it is adapted tofurnish signals having characteristics which are analogous to thosedefined herein.

Much that has been described in the foregoing and that is represented onthe drawing is characteristic of the invention. It is evident that oneskilled in the art can adduce all modifications of form and of detailusing his judgment, without departing from the scope of the invention.

I claim:

I. A testing device for measuring the response time of transistorizeddifferential amplifier upon the application of a transient signal to oneof two signal input terminals of said amplifier, comprising incombination:

connection means providing access to a first and a second signal inputtenninal, to a signal output terminal and to a control input terminal ofan amplifier to be tested, said connection means further applyingsuitable voltages of proper polarity to said amplifier;

circuit means for coupling said second signal input terminal and saidsignal output terminal in an inverse feedback loop to effectively cancelthe unbalanced voltage between said two signal input terminals in theabsence of an input signal;

a generator of recurrent signal pulses connected to apply said signalpulses to said first signal input terminal of said amplifier, each pulsehaving a duration much shorter than its recurrence period; and

means for connecting said first signal input terminal and said signaloutput terminal of the amplifier under test to a visual testinginstrument.

2. The testing device of claim 1, wherein said circuit means comprises asecond differential amplifier providing a high gain and having a firstinput terminal connected to said signal output terminal of the amplifierunder test, having a second input terminal receiving a comparisonvoltage, and having an output terminal connected through a voltagedivider to said second signal input terminal of the amplifier undertest.

3. A testing device for measuring the response time of transistorizeddifferential amplifier upon the application of a transient signal to oneof two signal input terminals of said amplifier, comprising incombination:

connection means providing access to a first and a second signal inputterminal, to a signal output terminal and to a control input terminal ofan amplifier to be tested, said connection means further applyingsuitable voltages of proper polarity to said amplifier;

circuit means for coupling said second signal input terminal and saidsignal output terminal in an inverse feedback loop to effectively cancelthe unbalanced voltage between said two signal input terminals in theabsence of an input signal, wherein said circuit means comprises asecond differential amplifier providing a high gain and having a firstinput terminal connected to said signal output terminal of the amplifierunder test, having a second input terminal receiving a comparisonvoltage, and having an output terminal connected through a voltagedivider to said second signal input terminal of the amplifier undertest;

a generator of recurrent signal pulses connected to apply said signalpulses to said first signal input terminal of said amplifier, each pulsehaving a duration much shorter than its recurrence period wherein saidsignal generator comprises a multistable device and a delay unit withreciprocal connections arranged such that said multistable devicegenerates at a plurality of output terminals thereof a sequence ofpulses, said sequence having a duration, termed measurement period,which is no greater than 1/25th the duration of a period of 55recurrence; and

means for connecting said first signal input terminal and said signaloutput terminal of the amplifier under test to a visual testinginstrument.

4. The testing device of claim 3, wherein when a first type-pulse isapplied to said first signal input terminal of the amplifier under testfrom a first output terminal of said multistable device, said first-typepulse terminating near a mid-point moment of each measurement period, amoment from which the response time can be observed at the out utterminal of the amplifier. 5. The testing device 0 claim 4, wherein asecond type pulse is applied to said second signal input terminal of theamplifier under test from a second output terminal of said multistabledevice and continues during at least the second half of said measurementperiod, and wherein a fourth output terminal of said multistable deviceis connected to apply to said control input terminal an inhibiting pulseduring said second half of said measurement period, said inhibitingpulse terminating before the end of said measurement period andinhibiting the operation of the amplifier under test.

6. A system for testing differential amplifiers, comprising the testingdevice of claim 5 and a dual-beam oscilloscope, wherein said outputterminal of the amplifier under test is connected to one of the verticalinput terminals of said oscilloscope, a first switch connects said firstsignal input terminal of said amplifier to the other vertical inputterminal of said oscilloscope, and a second switch connects a thirdoutput terminal of said multistable device to a synchronization inputterminal of said oscilloscope during first measurement of said responsetime.

7. The system of claim 6, wherein said first and second switches areplaced in a second position which connects the control input terminal ofthe amplifier under test to both of said other vertical input terminaland said synchronization input terminal of said oscilloscope during asecond measurement of response time.

8. A testing device for measuring the response time of a differentialamplifier, wherein said amplifier has a pair of input terminals and anoutput terminal, comprising in combination: signal generating meansconnectable to said amplifier for applying recurrent pulses to at leastone of said input terminals, time delay measuring means connectable tosaid one input terminal and to said output terminal for measuring thetime between each of said pulses and the consequent pulse delivered bysaid output terminal, and compensating means for applying a compensatingvoltage between said pair of input terminals to cancel the unbalancedvoltage between said terminal pair in the absence of input signals tosaid terminal pair.

0 l l III

1. A testing device for measuring the response time of transistorizeddifferential amplifier upon the application of a transient signal to oneof two signal input terminals of said amplifier, comprising incombination: connection means providing access to a first and a secondsignal input terminal, to a signal output terminal and to a controlinput terminal of an amplifier to be tested, said connection meansfurther applying suitable voltages of proper polarity to said amplifier;circuit means for coupling said second signal input terminal and saidsignal output terminal in an inverse feedback loop to effectively cancelthe unbalanced voltage between said two signal input terminals in theabsence of an input signal; a generator of recurrent signal pulsesconnected to apply said signal pulses to said first signal inputterminal of said amplifier, each pulse having a duration much shorterthan its recurrence period; and means for connecting said first signalinput terminal and said signal output terminal of the amplifier undertest to a visual testing instrument.
 2. The testing device of claim 1,wherein said circuit means comprises a second differential amplifierproviding a high gain and having a first input terminal connected tosaid signal output terminal of the amplifier under test, having a secondinput terminal receiving a comparison voltage, and having an outputterminal connected through a voltage divider to said second signal inputterminal of the amplifier under test.
 3. A testing device for measuringthe response time of transistorized differential amplifier upon theapplication of a transient signal to one of two signal input terminalsof said amplifier, comprising in combination: connection means providingaccess to a first and a second signal input terminal, to a signal outputterminal and to a control input terminal of an amplifier to be tested,said connection means further applying suitable voltages of properpolarity to said amplifier; circuit means for coupling said secondsignal input terminal and said signal output terminal in an inversefeedback loop to effectively cancel the unbalanced voltage between saidtwo signal input terminals in the absence of an input signal, whereinsaid circuit means comprises a second differential amplifier providing ahigh gain and having a first input terminal connected to said signaloutput terminal of the amplifier under test, having a second inputterminal receiving a comparison voltage, and having an output terminalconnected through a voltage divider to said second signal input terminalof the amplifier under test; a generator of recurrent signal pulsesconnected to apply said signal pulses to said first signal inputterminal of said amplifier, each pulse having a duration much shorterthan its recurrence period wherein said signal generator comprises amultistable device and a delay unit with reciprocal connections arrangedsuch that said multistable device generates at a plurality of outputterminals thereof a sequence of pulses, said sequence having a duration,termed ''''measurement period, '''' which is no greater than 1/25th theduration of a period of recurrence; and means for connecting said firstsignal input terminal and said signal output terminal of the amplifierunder test to a visual testing instrument.
 4. The testing device ofclaim 3, wherein when a first type-pulse is applied to said first signalinput terminal of the amplifier under test from a first output terminalof said multistAble device, said first-type pulse terminating near amid-point moment of each measurement period, a moment from which theresponse time can be observed at the output terminal of the amplifier.5. The testing device of claim 4, wherein a second type pulse is appliedto said second signal input terminal of the amplifier under test from asecond output terminal of said multistable device and continues duringat least the second half of said measurement period, and wherein afourth output terminal of said multistable device is connected to applyto said control input terminal an inhibiting pulse during said secondhalf of said measurement period, said inhibiting pulse terminatingbefore the end of said measurement period and inhibiting the operationof the amplifier under test.
 6. A system for testing differentialamplifiers, comprising the testing device of claim 5 and a dual-beamoscilloscope, wherein said output terminal of the amplifier under testis connected to one of the vertical input terminals of saidoscilloscope, a first switch connects said first signal input terminalof said amplifier to the other vertical input terminal of saidoscilloscope, and a second switch connects a third output terminal ofsaid multistable device to a synchronization input terminal of saidoscilloscope during first measurement of said response time.
 7. Thesystem of claim 6, wherein said first and second switches are placed ina second position which connects the control input terminal of theamplifier under test to both of said other vertical input terminal andsaid synchronization input terminal of said oscilloscope during a secondmeasurement of response time.
 8. A testing device for measuring theresponse time of a differential amplifier, wherein said amplifier has apair of input terminals and an output terminal, comprising incombination: signal generating means connectable to said amplifier forapplying recurrent pulses to at least one of said input terminals, timedelay measuring means connectable to said one input terminal and to saidoutput terminal for measuring the time between each of said pulses andthe consequent pulse delivered by said output terminal, and compensatingmeans for applying a compensating voltage between said pair of inputterminals to cancel the unbalanced voltage between said terminal pair inthe absence of input signals to said terminal pair.